出版教材
中心藏书| 编号 | SH021 |
|---|---|
| 书名 | Vdhl Modeling for Digital Design Synthesis |
| 作者 | Yu-Chin Hsu. Kevin F. Tsai,Jessie T. Liu,Eric S. L |
| 出版社 | Kluwer Academic Pub |
| 出版时间 | 1995年 |
| 类别 | 教学参考 |
| 状态 | 正常 |
| 简介 | 1.Introduction 2.Basic Structures in VHDL 3.Types,Operators and Expressiona 4.Sequential Statements 5.Concurrent Statements 6.Subprograms and Packages 7.Modeing at the Structural Level 8.Modeing at the RT Level 9.Modeing at the FSMD Level 10Modeing at the Algorithmic Level 11.Memories 12.VHDL Systhesis 13.Writing Efficient VHDL Descriptions 14.Practicing Designs |
